On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices

Reconfigurable devices like Configurable Systems on a Chip (CSoCs) have the ability to exchange parts of hardware during runtime. Multimedia applications often require computing power and often can be accelerated by specific hardware circuits. In this contribution we present the effect of hardware acceleration in reconfigurable devices. We introduce a new model of adaptive processors and describe its basic principle of operation. The model allows runtime variations of the type and number of functional units (including application specific FUs) as well as variations of the communication structure. Then, we discuss our multimedia kernel Inverse Discrete Cosine Transformation (IDCT) and the ability of shifting different parts of the IDCT into hardware. Simulation results show that hardware acceleration of multimedia operations in an adaptive processor leads to significant performance gains and therefore reduces energy consumption.