Charge pump based PLL design for IEEE 1394b PHY

This work describes a charge pump based phase-locked loop (PLL) employed in IEEE 1394b physical (PHY) system. The proposed PLL has a third order, type-2 topology, and its voltage-controlled oscillator (VCO) is composed of 4-stage delay cells to provide four phases of 1-GHz signals. This PLL has been fabricated in a 0.13-μm CMOS technology with 1.2V power supply voltage. According to the measurement results, the locking time is less than 5 μs, the peak-peak jitter and the RMS jitter are 398ps and 60ps, respectively. The die area of the PLL is 0.12mm², and the total power consumption is 19mW.