Optimum boundary design for ultra-high speed interpolation and averaging ADC

An optimum boundary design method used in pre-amplifiers stage of interpolation and averaging flash ADC is demonstrated in this work. Without costing a large number of dummy amplifiers and consuming over-range voltage headroom, the proposed technique improves linearity error at the boundary of pre-amplifier offset averaging network. A prototype 8bit flash ADC achieves an 1GSPS sampling speed with a 430mA current consumption in 1.8V supply, the experimental result shows that this optimum method is suitable for high speed flash ADC with interpolation and averaging network.