A 14-bit 500MS/S low power time-interleaved analog-to-digital converter in 0.18-µM CMOS technology with background calibration

This paper presents a low power 14-bit 500 MS/s analog-to-digital converter (ADC) in 180 nm CMOS process. By interleaving two 250 MS/s pipelined sub-ADC on a single chip, an aggregate sample rate of 500 MS/s is achieved. Background calibration techniques are used for offset mismatch, gain mismatch, and phase mismatch calibration between time-interleaved sub-ADC channels. An analog delay cell is utilized for phase mismatch correction. Test results show that the ADC achieves a 62.4dB signal-to-noise plus distortion (SNDR) and 73.6dB spurious-free dynamic range (SFDR) performance, respectively, after calibration for a 15 MHz input. Total power consumption is 810 mW from a single 1.8-V supply.