A reusable architecture design and implementation for inverse quantization of MP3 decoding

As the low cost, low power and low complexity are key points of the consumer application requirements, we propose a novel hardware-oriented architecture of the inverse quantization (IQ) in this paper, one of the important units, in computational complexity and precision, for MPEG-1 layer III decoder. It achieves a high throughput with lower memory requirement and can be reused into other calculation environment. The proposed IQ module has been designed and implemented by using VLSI cell-based approach. With three-level pipeline architecture, the maximum operation frequency of the design is 60 MHz. For the IQ computation of one data sample, it requires 33-35 clock periods, so that provides 40% reductions compared to that performed on DSP. The die size is 2.2 times 2.2 mm² , including 18 K bits of internal SRAM, and has been manufactured in an umc 0.18 um 1 P6M CMOS process.