Analysis and design of double nesting gain boosted amplifier in 14 bits 50 MS/S pipeline ADC

Author

Yanwei Wu ; Xiaohong Peng ; Yang Dong ; Miao Liu

Author_Institution

VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

Because of high sampling rate and high resolution, pipeline ADC is widely used in system on chip (SOC). As sampling rate and resolution increasing, design difficulty is increasing. This paper analyzes restricts from amplifier in Pipeline ADC. By contrast with different amplifiers, this paper analyzes and designs a double nesting gain boosted amplifier in 14 bits 50 MS/s pipeline ADC. Under 1.2 V power supply, this amplifier achieves 103 dB DC gain, 1.34 GHz unity gain bandwidth, 88° phase margin. Transient simulation result shows a 45μV settling time error in 10 ns. The total consumption is 24 mW.

Keywords

CMOS integrated circuits; analogue-digital conversion; power amplifiers; double nesting gain boosted amplifier; frequency 1.34 GHz; gain 103 dB; pipeline ADC; power 24 mW; storage capacity 14 bit; system on chip; time 10 ns; unity gain bandwidth; voltage 45 muV; Abstracts; Boosting; Education; Simulation; System-on-chip; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021567

Filename

7021567