DocumentCode
242294
Title
A 16/17 prescaler based on novel TSPC 2/3 devider scheme
Author
Shilin Yan ; Song Jia ; Wenyi Tang ; Jiyu Chen ; Ziyi Wang ; Weiting Li
Author_Institution
Shenzhen Grad. Sch., Peking Univ., Shenzhen, China
fYear
2014
fDate
28-31 Oct. 2014
Firstpage
1
Lastpage
3
Abstract
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The proposed design technique is applied to a divide-by-2/3 unit, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 49% reduction of PDP is achieved by the proposed unit.
Keywords
clocks; frequency dividers; prescalers; PDP; TSPC prescaler; divide-by-2-3 unit; frequency divider; power consumption; true single-phase clock-based prescaler; Abstracts; Logic gates; Frequency Divider; Prescaler; TSPC;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4799-3296-2
Type
conf
DOI
10.1109/ICSICT.2014.7021575
Filename
7021575
Link To Document