Title :
A CMOS third-order 2-1 cascade sigma-delta modulator
Author :
Rui Liang ; Zhaohan Li ; Baijun Zhao ; Shuang Cui ; Gengyun Wang ; Yuchun Chang
Author_Institution :
Coll. of Electron. Sci. & Eng., Jilin Univ., Changchun, China
Abstract :
This paper describes a 0.18μm CMOS switched-capacitor 2-1 cascade sigma delta modulator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The modulator occupies an area of 0.14 mm2 and dissipates 9.9 mW from 3.3 V supply. The modulator clocked at 10 MHz and considering 4 kHz input sine wave. We can get a final 14 bit resolution and the modulator achieves an 85dB SNR.
Keywords :
CMOS digital integrated circuits; cascade networks; circuit optimisation; integrated circuit design; modulators; sigma-delta modulation; statistical analysis; CAD methodology; CMOS third-order cascade sigma-delta modulator; SNR; frequency 4 kHz; modulator hierarchy; power 9.9 mW; sine wave; size 0.14 mm; size 0.18 mum; statistical optimization; switched-capacitor sigma-delta modulator; voltage 3.3 V; Abstracts; CMOS integrated circuits; Clocks; Flip-flops; Frequency modulation; Switching circuits;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021581
