BIST-based digital design for IEEE 1394B PHY

Author

Zhang Wen ; HaiQi Liu ; Qiang Li

Author_Institution

Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

A Built-In Self Test (BIST) based digital design for IEEE 1394b Physical Layer (PHY) is presented. The proposed circuit fabricated in 0.13-μm CMOS technology is mainly composed of 8B/10B encoder/decoder block, I2C slave block, 2^nd-order low-pass digital filter, and BIST circuit. This circuit aims at reducing area and power consumption of the chip and meeting the testing needs of IEEE 1394b SerDes PHY, with I2C slave block and BIST system contribute to a more efficient way for chip testing. The die area of the digital circuit is 0.13mm², and the whole SerDes circuit occupies an area of 2.9×1.6mm².

Keywords

CMOS integrated circuits; IEEE standards; built-in self test; digital filters; integrated circuit design; integrated circuit testing; low-pass filters; low-power electronics; 8B/10B encoder/decoder block; BIST-based digital design; CMOS technology; I2C slave block; IEEE 1394b SerDes PHY; IEEE l394b Physical Layer; built-in self test; chip testing; power consumption; second-order low-pass digital filter; size 0.13 mum; Abstracts; Encoding; Frequency conversion; 8B/10B; Built-In Self Test (BIST); Firewire; IEEE 1394b; Serializer/Deserializer (SerDes);

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021584

Filename

7021584