A pipelined architecture for logic programming with a complex but single-cycle instruction set

An architecture that executes logic programs using fewer instruction cycles than hardware implementations of the Warren Abstract Machine or the Berkeley SPUR augmented with a Prolog coprocessor is described. This is achieved by balancing the characteristics of CISC (complex instruction set computer) and RISC (reduced instruction set computer) architectures. Specifically, this architecture provides support for the semantics of logic programs using complex instructions and multiple pipelined functional units. Examples of complex instructions include partial unify, push and load reference, pop and deference, and switch on type; all typically execute in a single clock cycle from a full pipeline. Conditional instruction execution reduces a branch frequency to 0.09%, which keeps the pipeline full and allows 16-way memory interleaving. Under these conditions, one LIBRA processor using 100 ns memory is estimated to execute nine million logical inferences per second