A true single-phase clocked full-adder using floating-gate MOS transistor

A new true-single-phase clocked (TSPC) full-adder using floating-gate MOS (FGMOS) transistor is presented. In this new design scheme, the logic tree for the sum-generate circuit is realized using only an n-channel multiple-input FGMOS transistor, and the logic for the carry-generate circuit is realized using a complementary FGMOS-based inverter. By using FGMOS transistors, the circuit structure can be dramatically simplified. Since the voltage signals are easy to be added by means of floating gate in FGMOS transistor, a summation signal treated as a medium variable is employed in the circuit design. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed circuits. For comparison, the power consumption and the output delay of the proposed TSPC full-adder are measured during the simulations.