DocumentCode
2423380
Title
Efficient algorithms for microprocessor testing
Author
Joshi, Bharat S. ; Hosseini, Seyed H.
Author_Institution
Dept. of Math. & Comput. Sci., Western Carolina Univ., Cullowhee, NC, USA
fYear
1998
fDate
19-22 Jan 1998
Firstpage
100
Lastpage
104
Abstract
In this paper, the authors present simple yet efficient fault detection algorithms for microprocessor systems. They propose test generation algorithms to generate test sequences. These test sequences are used by the proposed testing algorithms. The test generation algorithms are divided into two classes. The data processing unit test generator generates tests for every functional block in the ALU while the control unit test generator generates tests for fault detection in instruction and register decoding, buses, and registers. The authors show that the major advantage of the test generation algorithm for the data processing unit is that it ignores the implementation details and thus it can be used for a wide spectrum of technologies. They also show analytically that the running time of the control unit test algorithm is in O(n) where n is the number of instructions. The simulation techniques used and the experimental results obtained are presented. The concept of functionality tests has been strictly maintained. The simulation results suggest that the technique is independent of the implementation. This technique can be easily applied to larger multiprocessor systems where each processor can perform quick yet efficient tests on a subset of the microprocessors
Keywords
computer testing; fault diagnosis; integrated circuit testing; microcomputers; ALU; algorithm efficiency; buses; data processing unit; experimental results; fault detection algorithms; instruction decoding; microprocessor systems; microprocessor testing algorithms; register decoding; registers; running time; simulation techniques; test generation algorithms; Algorithm design and analysis; Arithmetic; Data processing; Decoding; Fault detection; Hardware; Logic testing; Microprocessors; Multiprocessing systems; Performance evaluation; Switches; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability and Maintainability Symposium, 1998. Proceedings., Annual
Conference_Location
Anaheim, CA
ISSN
0149-144X
Print_ISBN
0-7803-4362-X
Type
conf
DOI
10.1109/RAMS.1998.653641
Filename
653641
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