Title :
High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation
Author :
Wen-Quan He ; Yuan-Ho Chen ; Shyh-Jye Jou
Author_Institution :
Electron. Eng. Dept., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-μm CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.
Keywords :
CMOS logic circuits; error compensation; multiplying circuits; probability; CMOS process; conditional probability; dynamic error compensation circuit; expected probability; fixed-width booth multiplier; high accuracy Booth multiplier; power 6.7 mW; size 0.18 mum; word length 16 bit; Accuracy; Adders; Arrays; Computer simulation; Integrated circuit modeling; Picture archiving and communication systems; Power demand; Booth encoder; dynamic error-compensation; fixed-width multiplier; mathematical probable model;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2015.2440731
