DocumentCode
2423506
Title
ACCGen: An Automatic ArchC Compiler Generator
Author
Auler, Rafael ; Centoducatte, Paulo Cesar ; Borin, Edson
Author_Institution
Comput. Syst. Lab., Univ. of Campinas-UNICAMP Campinas, Sao Paulo, Brazil
fYear
2012
fDate
24-26 Oct. 2012
Firstpage
278
Lastpage
285
Abstract
The current level of circuit integration led to complex designs encompassing full systems on a single chip, known as System-on-a-Chip (SoC). In order to predict the best design options and reduce the design costs, designers are required to perform a large design space exploration on early stages of the design. To speed up this process, Electronic Design Automation (EDA) tools are employed to model and experiment with the system. ArchC is an "Architecture Description Language" (ADL) and a set of tools that can be leveraged to automatically build SoC simulators based on high-level system models, enabling easy and fast design space exploration in early stages of the design. Currently, ArchC is capable of automatically generating hardware simulators, assemblers, and linkers for a given architecture model. In this work, we present ACCGen, an automatic Compiler Generator for ArchC, the missing link on the automatic generation of compiler tool chains for ArchC. Our experimental results show that compilers generated by ACCGen are correct for Mibench applications. They compare, as well, the generated code quality with LLVM and gcc, two well-known open-source compilers. We also show that ACCGen is fast and has little impact on the design space exploration turnaround time, allowing the designer to, using an easy and fully automated workflow, completely assess the outcome of architectural changes in less than 2 minutes.
Keywords
circuit simulation; compiler generators; electronic design automation; integrated circuit design; program assemblers; public domain software; specification languages; system-on-chip; ACCGen; ADL; Architecture Description Language; EDA tool; LLVM; Mibench application; SoC simulator; architecture model; assembler; automatic ArchC compiler generator; circuit integration; complex design; design cost reduction; design space exploration; electronic design automation; generated code quality; hardware simulator; high-level system model; open-source compiler; system-on-a-chip; Assembly; Computer architecture; Generators; Hardware; Registers; Semantics; Syntactics; ADL; Automatic Compiler Generation; Code Generator Generator; Compiler Backend; EDA;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE 24th International Symposium on
Conference_Location
New York, NY
ISSN
1550-6533
Print_ISBN
978-1-4673-4790-7
Type
conf
DOI
10.1109/SBAC-PAD.2012.33
Filename
6374799
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