Noise aware clock tree synthesis for 3D ICs

The paper focuses on mitigating the noise coupling effects induced by through-silicon via (TSV) during clock tree synthesis (CTS) of 3D ICs and minimizing TSV count and wire length. Firstly, we utilize a density-based clustering method on the clock sinks, and then construct a local topology for each cluster with MMM+DME method. In this step, we use K-DIST algorithm to improve DBSCAN clustering method. Secondly, we construct global tree topology for unsorted sinks and root nodes of clusters with our improved NNG-based method, with consideration of delay induced by TSV. In the end, we finish routing and buffering with DME-3D method. The results of the experiments shows that our approach can achieve a balanced distribution of TSVs and ensure few sinks located near TSVs by density-based clustering, which mean the goal of mitigation of TSV coupling effects is reached. Compared with related work with similar CTS flows, our method significantly reduces TSV count and total wire length.