An efficient MV prediction VLSI architecture for H.264 video decoder

Variable block sizes, complex spatial motion vector prediction, particular skip and direct temporal MV prediction contribute to superior performance of H.264 standard. However, high irregularity of its MV prediction algorithm also makes efficient hardware implementation challenging. In this paper, an efficient VLSI architecture is proposed for irregular MV prediction implementation. Complex control logic is simplified by regularly lookuping control parameters in a predefined table. The parameters of the current MB and neighboring blocks are also initialized and updated regularly. Pipeline and parallelism are jointly employed in the proposed architecture to shorten the processing time and minimize hardware consumption. Moreover, highly regular architecture also simplifies the function verification considerably. Simulation results verify the effectiveness of the proposed design.