Accurate energy dissipation and thermal modeling for nanometer-scale buses

With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important, and this necessitates the development of accurate models to explore these effects during design stage, with simulators and using realistic workloads. In this work, we present a unified nanometer-scale bus energy dissipation and thermal model that helps designers monitor energy dissipation and temperature rise in individual wires during dynamic simulation. In addition to self capacitance, our model incorporates the effects of capacitive coupling between adjacent as well as non-adjacent pairs of wires on switching energy, effect of repeater insertion, and the effect of lateral heat transfer between adjacent wires, all of which have been ignored in earlier models. Next, using our integrated model in a first-of-its-kind study, we study energy dissipation and thermal characteristics of instruction and data address buses with traces obtained from standard SPEC CPU2000 benchmarks and using technology parameters for various nanometer technology nodes from the ITRS road-map. We also evaluate the effect of some well-known low-power bus design schemes on bus line energy dissipation.