Hardware implementation of transform and quantization for AVS encoder

Multimedia applications need larger and larger bandwidth. The only way to face the demands is to provide better and faster video compression standard. Thus, AVS is created in China. To address the need for hardware acceleration of its computationally intensive parts, high throughput hardware architectures for fast computation of the 2-D Transform Quantization Inverse Quantization and Inverse Transform are presented in this paper. In addition, two high performance system architectures are presented. The proposed hardware architectures are incorporated into two different hardware systems implemented on a Virtex 4 Pro FPGA. Simulation results show that both two hardware system architectures that are incorporated proposed architectures could provide satisfactory performances.