ESD clamp protection structure with current mirror trigger circuit in submicron CMOS technology

Author

Xiaozong Huang ; Luncai Liu ; Wengang Huang ; Fan Liu ; Jun Luo ; Dongmei Zhu

Author_Institution

Analog IC Design Center, SISC, Chongqing, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

An ESD clamp protection structure with current mirror for capacitor boosting was proposed in this paper. For the power rail protection, silicon-control-rectifier (SCR) is a better choice than the BIGFET as main ESD clamp device, which can provide better ESD robustness with smaller area and lower leakage current. The area of protection structure is reduced further for the utility of capacitor boosting technique. The trigger performance of the power rail clamp device was verified in the commercial CMOS process with featured size of 0.18°m. The total area of 50°m×50°m was achieved. The failure phenomenon in the measurement was also discussed for further improvement in this paper.

Keywords

CMOS integrated circuits; current mirrors; electrostatic discharge; failure analysis; leakage currents; thyristors; trigger circuits; BIGFET; ESD clamp protection structure; SCR; capacitor boosting technique; complementary metal oxide semiconductor; current mirror trigger circuit; electrostatic discharge; leakage current; power rail clamp device; power rail protection; silicon-control-rectifier; size 0.18 mum; submicron CMOS technology; trigger performance; Abstracts; Clamps; Electrostatic discharges; Optical variables measurement; Robustness; Thyristors; Transient analysis; Capacitor boosting; SCR; failure analysis; power rail protection;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021662

Filename

7021662