DocumentCode
242483
Title
Area saved and clamp efficient multi-RC-triggered power clamp circuit for on-chip ESD protection
Author
Haibing Guo ; Yuan Wang ; Guangyi Lu ; Song Jia ; Xing Zhang
Author_Institution
Shenzhen Grad. Sch., Peking Univ., Shenzhen, China
fYear
2014
fDate
28-31 Oct. 2014
Firstpage
1
Lastpage
3
Abstract
An improved multi-RC-triggered power clamp circuit is presented in this paper. It could save more silicon area than prior designs while clamp the VDD more efficiently. The three-stage RC-trigger circuit design can fast close up the clamp MOSFET when it is mis-triggered in a certain situation. Mis-trigger immunity down to 2μs power-up rise time is also achieved for a designed clamp MOSFET width of 1920μm.
Keywords
MOSFET; RC circuits; electrostatic discharge; elemental semiconductors; silicon; trigger circuits; Si; area saved clamp efficient circuit; clamp MOSFET; electrostatic discharge protection; mis-trigger immunity; multiRC-triggered power clamp circuit; on-chip ESD protection; resistor-capacitor circuit; silicon area; size 1920 mum; three-stage RC-trigger circuit; while clamp; Clamps; Digital audio players; Electrostatic discharges; Leakage currents; Logic gates; MOS devices; Simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4799-3296-2
Type
conf
DOI
10.1109/ICSICT.2014.7021665
Filename
7021665
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