3D self testing with Spidergon STNoC

Summary form only given. 3D integration technology allows the stacking of different chips and devices in a single package. This technology is a very attractive option for many advanced consumer products meeting specifications of the next generation of market key drivers such as mobile phones, set-top-boxes and HDTV. By replacing single chip packages with 3D devices, higher transistor density and low power saving are achieved, data travel distances shortens, the manufacturing cost decreases through die reuse generalization. The maximum benefit is obtained from the use of heterogeneous and highly specialized technologies, and the possibility to make the optimal partitioning early in the design process. This presentation aims at providing novel system solutions to enhance testing with NoC when used in 3D SoCs. In addition, the presentation will address how Spidergon STNoC handling tests with 3D SoCs with multiple power domains and voltage islands.