DocumentCode :
2424951
Title :
Ordering of analog specification tests based on parametric defect level estimation
Author :
Akkouche, Nourredine ; Mir, Salvador ; Simeu, Emmanuel
Author_Institution :
Reliable Mixed-signal Syst. Group, TIMA Lab., Grenoble, France
fYear :
2010
fDate :
19-22 April 2010
Firstpage :
301
Lastpage :
306
Abstract :
This paper presents an approach for ordering analog specification (or functional) tests that is based on a statistical estimation of parametric defect level. A statistical model of n specification tests is obtained by applying a density estimation technique to a small sample of data (obtained from the initial phase of production testing or through Monte-Carlo simulation of the design). The statistical model is next sampled to generate a large population of synthetic devices from which specification tests can be ordered according to their impact on defect level by means of feature selection techniques. An optimal order can be obtained using the Branch and Bound method when n is relatively low. However, for larger values of n, heuristic methods such as genetic algorithms and floating search must be used which do not guarantee an optimal order. Since the value of n can reach several hundreds for advanced analog integrated devices, we have studied a heuristic algorithm that considers combinations of subsets of the overall test set. These subsets are easier to model and to order and a heuristic approach is used to form an overall order. This test ordering approach is evaluated for different artificial and experimental case-studies, including a fully differential operational amplifier. These case-studies are simple enough so that it is possible to compare the results obtained with the algorithm with an expected reference order.
Keywords :
Monte Carlo methods; analogue integrated circuits; integrated circuit testing; parameter estimation; statistical analysis; Monte-Carlo simulation; advanced analog integrated devices; analog specification test ordering; branch and bound method; density estimation technique; feature selection techniques; floating search algorithm; fully differential operational amplifier; genetic algorithms; heuristic methods; parametric defect level estimation; statistical estimation; synthetic devices; test ordering approach; Circuit testing; Cost function; Data engineering; Differential amplifiers; Genetic algorithms; Heuristic algorithms; Operational amplifiers; Production; System testing; Very large scale integration; Analog test; density estimation; feature selection; test metrics; test ordering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
ISSN :
1093-0167
Print_ISBN :
978-1-4244-6649-8
Type :
conf
DOI :
10.1109/VTS.2010.5469546
Filename :
5469546
Link To Document :
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