Parallel optimistic logic simulation with event lookahead

Parallel discrete event simulation (PDES) on general-purpose machines can reduce the logic simulation time for large circuits considerably. However, it generates more events than necessary for certain high activity circuits and produces inconsistent execution times over different circuits. This is because glitches contribute to a sizable portion of events during a simulation. The proposed Event-lookahead Time Warp (ETW) algorithm can look ahead, combine and execute multiple events at each gate optimistically, and recover from an error by using a rollback mechanism as used in the original time warp algorithm. As a result, it reduces unnecessary events and produces more consistent execution times and reasonable speedups