DocumentCode :
2424970
Title :
A novel hybrid delay testing scheme with low test power, volume, and time
Author :
Chen, Zhen ; Seth, Sharad ; Xiang, Dong
Author_Institution :
Dept. of Comp. Sci. & Techn., Tsinghua Univ., Beijing, China
fYear :
2010
fDate :
19-22 April 2010
Firstpage :
307
Lastpage :
312
Abstract :
Test power, volume, and time are the major test cost parameters that must be minimized while achieving the desired level of fault coverage. Unlike prior research in delay fault testing that has focused on at most two test cost parameters, the hybrid (LOS+LOC) scheme proposed here simultaneously considers all three cost parameters and achieves better fault coverage than prior schemes, as demonstrated by experimental results. A factor of (n/logn) reduction in test power is achieved by the use of a nonlinear double-tree-scan (DTS) structure instead of linear scan chain of length n. Concomitantly, by exploiting the permutation feature of DTS, whereby the same test data can be loaded in multiple ways, we also achieve substantial reductions in the test-data volume. By incorporating the Illinois scan (ILS) within this framework, we minimize not only the test time but also achieve further reductions in test-data volume.
Keywords :
fault diagnosis; integrated circuit testing; DTS; Illinois scan; fault coverage; hybrid delay testing scheme; nonlinear double-tree-scan structure; test-data volume; Automatic test pattern generation; Circuit faults; Circuit testing; Clustering algorithms; Computer science; Costs; Delay effects; Power engineering and energy; Software testing; Very large scale integration; Double tree scan; Fault coverage; Hybrid delay test; Nonlinear scan architecture; Test cost;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
ISSN :
1093-0167
Print_ISBN :
978-1-4244-6649-8
Type :
conf
DOI :
10.1109/VTS.2010.5469547
Filename :
5469547
Link To Document :
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