Power delivery dynamics and its impact on silicon validation

Summary form only given.The drive to low power regimes has highlighted the impact of power delivery dynamics on the operation and testing of the die. In normal functional mode, the transient draw of transistor currents will create scenarios that, via voltage droop, may impact the maximum operational frequency of the die. The same is true for functional testing. Even a need to replicate these effects for scan-based testing is not easily done without understanding both the dynamics of the power delivery as well as its impact on frequency during functional operation and functional testing. In this talk, power delivery dynamics will be discussed. Global and local voltage fluctuations will be mapped into the roughly four different kinds of voltage droops including the frequencies associated with each. It will be shown how decoupling capacitor placement either on a die or externally on the package will affect each of the kinds of voltage droops described. A description of the different die events, in either functional or scan mode, which can set up frequencies to impact each of the kinds of voltage droops, will be given. It will be shown that post-silicon functional speed-paths are often a clear function of the voltage droop dynamics. The second part of the problem consists in creating tests to excite the correct sequence of voltage droops to cause impact on the total droop seen by the transistors. We will discuss an early flow based on machine abstraction, charge assignment to reflect current draw, and charge sequence optimization to enable one to accomplish test-generation for droop post-silicon and the application of this flow on a major microprocessor. Post-silicon voltage measurements will be used to demonstrate the complexity needed to achieve a large droop impact in a short test which would be equivalent to running multiple functional tests.