DocumentCode
2425143
Title
Rapid implementation of DSP algorithms for algorithm evaluation: a decimation filter example
Author
Israsena, Pasin ; Wongnamkum, Sitthipong
Author_Institution
Nat. Electron. & Comput. Technol. Center (NECTEC), Pathumthani
fYear
2008
fDate
7-9 July 2008
Firstpage
180
Lastpage
184
Abstract
This paper discuses a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time. A decimation filter for analog-to-digital conversion is implemented as an example, with the results analyzed and compared to the more conventional RTL coding and synthesis approach.
Keywords
analogue-digital conversion; digital filters; digital signal processing chips; field programmable gate arrays; DSP algorithm; FPGA hardware; algorithm evaluation; analog-to-digital conversion; decimation filter; rapid implementation; Algorithm design and analysis; Delta modulation; Digital modulation; Digital signal processing; Digital signal processing chips; Field programmable gate arrays; Filters; Hardware; Noise shaping; Software;
fLanguage
English
Publisher
ieee
Conference_Titel
Audio, Language and Image Processing, 2008. ICALIP 2008. International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-1723-0
Electronic_ISBN
978-1-4244-1724-7
Type
conf
DOI
10.1109/ICALIP.2008.4590131
Filename
4590131
Link To Document