Special session 8C: Panel EDA for analog DFT/ATPG – will SoC cost pressures make this a reality?

With the advent of ultra large scale integration on silicon, computing and communication devices are trending towards a system-on-chip (SoC) on a single die integrating several processor cores, several types of high-speed I/O interfaces and analog components. The integration of such diverse components along with associated loss of controllability and/or observability of each component is already creating significant issues for reliable test of such chips.