DocumentCode :
2425215
Title :
Special session 8C: Panel EDA for analog DFT/ATPG – will SoC cost pressures make this a reality?
Author :
Sinha, Arani
Author_Institution :
Advanced Micro Devices
fYear :
2010
fDate :
19-22 April 2010
Firstpage :
259
Lastpage :
259
Abstract :
With the advent of ultra large scale integration on silicon, computing and communication devices are trending towards a system-on-chip (SoC) on a single die integrating several processor cores, several types of high-speed I/O interfaces and analog components. The integration of such diverse components along with associated loss of controllability and/or observability of each component is already creating significant issues for reliable test of such chips.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA, USA
ISSN :
1093-0167
Print_ISBN :
978-1-4244-6649-8
Type :
conf
DOI :
10.1109/VTS.2010.5469561
Filename :
5469561
Link To Document :
بازگشت