High level synthesis of a Front End filter and DSP engine for analog to digital conversion – a case study

We present the design of a Sine Cubed Decimator and of a Front End DSP Engine for Analog to Digital Conversion using high-level synthesis. The input language was SystemC and the High Level Synthesis tool was Cadence\´s C to Silicon compiler. Area and timing results, as well as comments on the overall experience, are also presented. The main motivation for exploring High Level Synthesis (HLS) at Freescale was the desire to increase design and verification productivity, including reducing coding / design entry time, reducing verification time, increasing opportunities for microarchitectural exploration, and increasing opportunities for design re-use by using object oriented programming techniques. Additionally, in order to incorporate HLS in a production environment other characteristics such quality of results comparable to an RTL design flow (meeting timing and a 20% area overhead was considered acceptable) and seamless integration within the current RTL synthesis place and route design flow were also evaluated. Two different design approaches were followed. First, we attempted to modify a pure simulation model into code acceptable by the High Level Synthesis Tool. This approach was soon discarded since it led neither to productivity gains nor good quality of results. We then rewrote the models in an "implementation neutral" manner, such that we could target different platforms (e.g., ASICs or FPGAs). After completing the design we evaluated the costs/benefits of adopting high-level synthesis and arrived at the following conclusions: a ) The quality of results was acceptable (all blocks met timing, and the area was within acceptable bounds of hand-written RTL). b) There were substantial improvements in simulation time when compared to RTL simulation, c) Even though this was the first System C design experience for some of the team\´s members, the coding time for both designs was substantially less than the coding time for equivalent RTL and d) Once design was finish- - ed, the High Level Synthesis tool allowed us to explore different microarchitectures in order to obtain the best acceptable compromise between area, timing, and power while delivering the required latency and throughput of the block.