Title :
Design of key technology in reflective memory network communication module
Author :
Yong Chen ; Yan Wang ; Xiaofeng Tang ; Wenbo Wu
Author_Institution :
Bejing Oil Res. Inst., Beijing, China
Abstract :
On the hardware platform of Distributed Real-Time Simulation, a communication module based on reflective memory network was realized in FPGA. As an infrastructure module, it could be integrated with other modules seamlessly. Under the speed-first rules, DMA engine in PCI Master mode was designed, and 64bits/32bits bus compatibility was realized. In order to solve the competition problems during network and memory access, the Arbiter strategy based on adjustable time slice was proposed. In addition, network command packets of higher priority were introduced to fit practical simulation requirements, including the interrupts issue.
Keywords :
asynchronous circuits; field programmable gate arrays; integrated memory circuits; modules; Arbiter strategy; DMA engine; FPGA; PCI master mode; adjustable time slice; bus compatibility; distributed real-time simulation; interrupts issue; key technology design; memory access; network command packet; reflective memory network communication module; speed-first rule; Educational institutions; Electronics packaging; Engines; Field programmable gate arrays; Microcomputers; Optical fiber networks; DMA engine; FPGA; arbiter strategy; reflective memory network;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021690
