A line based two dimensional cache design for interpolation in H.264/AVC decoder

Bandwidth is a valuable resource related to power consumption and operation cycles in VLSI implementation. H.264/AVCpsilas quarter pixels interpolation scheme has become bandwidth bottleneck during decoding process. This paper presents a line based two dimensional on-chip cache, which can achieve less than 6% of redundant fetch rate compared to ideal model assuming no redundant fetch at all. Compared to other schemes [2],[3], proposed design can also greatly reduces redundant fetch rate and improves around 20% of data bus utilization rate with acceptable hardware expense.