DocumentCode :
24255
Title :
Analysis for the integration feasibility of OpenSPARC T1 and a Petri Nets processor to form a system with hardware synchronization capability
Author :
Nonino, J. ; Furey, I. ; Pisetta, C.R. ; Micolini, Orlando
Volume :
11
Issue :
1
fYear :
2013
fDate :
Feb. 2013
Firstpage :
60
Lastpage :
64
Abstract :
OpenSPARC T1 is the open source version of the UltraSPARC T1 processor developed by Sun Microsystems. XiIinx development kit with a Virtex-5 gives the chance to test and change it. We analyzed the performance of the parts of OpenSPARC and Petri processor. We have considered several possibilities of adding a Petri processor to improve performance of processes that require synchronization.
Keywords :
Petri nets; microprocessor chips; synchronisation; OpenSPARC T1 processor; Petri nets processor; UltraSPARC T1 processor; Virtex-5; XiIinx development kit; hardware synchronization; integration feasibility; Field programmable gate arrays; Hardware; Microprogramming; Monitoring; Multicore processing; Software; Sun; FPGA; OpenSPARC T1; Petri Nets; Synchronization; VIRTEX-5;
fLanguage :
English
Journal_Title :
Latin America Transactions, IEEE (Revista IEEE America Latina)
Publisher :
ieee
ISSN :
1548-0992
Type :
jour
DOI :
10.1109/TLA.2013.6502778
Filename :
6502778
Link To Document :
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