Evaluating yield and testing impact of sub-wavelength lithography

Sub-wavelength lithography uses light waves that have a longer wavelength than the feature size that is being printed. Image distortions are an inevitable consequence of this situation, even after resolution enhancement techniques have been applied. This paper studies in detail how the image distortion in a fabricated IC can impact test and critical-area yield loss. Particularly, lithography simulation is performed on the desired pattern to predict the printed (distorted) pattern. The impact on critical-area yield loss is studied using both the desired pattern and the printed pattern. Similarly, the impact on test is studied using inductive fault analysis on both the desired pattern and the printed pattern. Even under the assumption of the best process conditions, experiment results indicate that the difference in misdirected test effort can be as large as 8.0% and the difference in the critical-area yield calculations is about 3.4% for a large design. The more accurate analysis requires a runtime increase of 5X on average.