Notice of Violation of IEEE Publication PrinciplesA -5OdBc Spur 0.13μm CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture

Notice of Violation of IEEE Publication Principles

"A -5OdBc Spur 0.13 μm CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture"
by Maxim, A.; Poorfard, R.; Kao, J.;
in the Proceedings of the 2007 IEEE Radio and Wireless Symposium,
Jan. 2007 Page(s):427-430

After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici D. Smith S. Dupue

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A fully-integrated 0.13 μm CMOS ring oscillator based PLL for digital low-IF DVB-S/S2 satellite TV tuner is presented. An attenuator loop filter reduces the oscillator gain, helping both front-end noise and spur rejection, while a noiseless resistor multiplication feed-forward architecture allows the on-chip integration of the loop filter capacitance. Eliminating oscillator inductors lead to a significant die area reduction and a low sensitivity to magnetic coupling, allowing the integration of a large digital core on the same die with the sensitive RF front-end. A multi-regulator biasing- architecture was used to minimize the supply spur injection. PLL specifications include: <1.3°_rms double-sided integrated phase noise from 10 KHz to 22.5 MHz, <-60 dBc reference spurs, <-50 dBc supply coupled spurs, 0.3 mm² die area and 40 mA supply current from a 3.3 V supply