Instruction set architecture of the determined memory access processor

Author

Melnyk, Anatoly ; Salo, Andriy

Author_Institution

Dept. of Comput. Eng., Lviv Polytech. Nat. Univ., Ukraine

fYear

2003

fDate

18-22 Feb. 2003

Firstpage

198

Lastpage

199

Abstract

There are lot of applications that demand intensive data streams processing in real time nowadays. These tasks are usually performed by dedicated or algorithm-specific computer systems. Such systems design is quite complicated and laborious process while time-to-market is critical. So there is a need for the computer-aided dedicated systems design methods development. In given work instruction set architecture of the determined memory access processor is proposed. Such a processor usage will grant very short terms of application-specific systems design.

Keywords

parallel architectures; reconfigurable architectures; reduced instruction set computing; special purpose computers; RISC architecture; application-specific systems design; computer architecture; computer-aided dedicated systems design; data-independent algorithms; determined memory access processor; embedded computer systems; instruction set architecture; intensive data streams; memory model; parallel reconfigurable processor; running accumulator; Computer aided instruction; Computer architecture; Counting circuits; Energy consumption; Read-write memory; Registers; VLIW; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of

Print_ISBN

966-553-278-2

Type

conf

DOI

10.1109/CADSM.2003.1255028

Filename

1255028