Statistical modeling of the program/erase cycling acceleration of low temperature data retention in floating gate nonvolatile memories

Charge leakage from nonvolatile memory floating gates at temperatures below 200°C has been observed by many authors. The leakage, which we refer to as low temperature data retention (LTDR), is activated by program/erase (P/E) cycling of a flash memory array. LTDR can be observed as tailbits in experimental threshold voltage distributions. In this paper, we describe cycling acceleration using experimental data across a wide range of P/E cycles from 10 to 1x10⁵. To account for the random nature of LTDR, we apply a statistical modeling methodology using data from large sample experiments.