DocumentCode
2426151
Title
Impact of multiple input switching on delay test under process variation
Author
Wu, Sean H. ; Chakravarty, Sreejit ; Wang, Li.-C.
Author_Institution
ECE Dept., Univ. of California - Santa Barbara, Santa Barbara, CA, USA
fYear
2010
fDate
19-22 April 2010
Firstpage
87
Lastpage
92
Abstract
Multiple input switching (MIS) on off-path inputs is known to increase the delay through a gate. However, due to the complexity of incorporating MIS in timing analysis, design flows typically ignore the effect of MIS. Test tools also do not attempt to maximize the off-path switching to maximize delays through a path. In this paper we study the impact of not maximizing the switching on the off-path inputs in different process corners. We present quantitative data to estimate the test escape or mis-binning that could result if MIS is not considered as part of our path-delay test generation process.
Keywords
automatic test pattern generation; integrated circuit testing; design flows; multiple input switching; off-path inputs; path-delay test generation; process variation; timing analysis; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Circuit testing; Clocks; Delay effects; Libraries; Robustness; Switches; Timing; multiple input switching; path delay test; speed binning;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2010 28th
Conference_Location
Santa Cruz, CA
ISSN
1093-0167
Print_ISBN
978-1-4244-6649-8
Type
conf
DOI
10.1109/VTS.2010.5469606
Filename
5469606
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