DocumentCode
2426241
Title
A drain avalanche hot carrier lifetime model for n- and p-channel MOSFETs
Author
Koike, Nono ; Tatsuuma, Kenichiro
Author_Institution
ULSI Process Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
fYear
2002
fDate
2002
Firstpage
86
Lastpage
92
Abstract
A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as τ(Id/W)2∝(Isub/Id)-m. The formula is different from the conventional τId/W-Isub/Id model in that the exponent of Id/W is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical τ-Isub/W model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low energy carriers to create the damage.
Keywords
MOSFET; electron traps; electron-hole recombination; hot carriers; semiconductor device models; semiconductor device reliability; carrier critical energies; drain avalanche; hot carrier lifetime model; interface trap generation; low energy carriers; n-channel MOSFETs; oxide band edge tailing; p-channel MOSFETs; physical basis; recombination; Charge carrier processes; Circuit simulation; Degradation; Drain avalanche hot carrier injection; Electron traps; Hot carriers; MOSFET circuits; Radiative recombination; Spontaneous emission; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium Proceedings, 2002. 40th Annual
Print_ISBN
0-7803-7352-9
Type
conf
DOI
10.1109/RELPHY.2002.996614
Filename
996614
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