Title :
Detecting NBTI induced failures in SRAM core-cells
Author :
Fonseca, R. Alves ; Dilillo, L. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Badereddine, N.
Author_Institution :
Lab. d´´Inf., de Robot. et de Microelectron. de Montpellier - LIRMM, Univ. de Montpellier II, Montpellier, France
Abstract :
Negative Bias Temperature Instability (NBTI) is a degradation phenomenon that occurs in PMOS transistors during circuit lifetime. Recent works have proposed transistor level and circuit level models that allow designers to deal with such phenomenon. Based on these models and taking into account Random Dopant Fluctuation (RDF), we study the possibility of detecting SRAM core-cells that are prone to NBTI failures during post-production test. For this purpose, we introduce a statistical simulation method that allows estimating the amount of NBTI affected core-cells that pass or fail under given test conditions. Supply voltage, temperature, word line pulse width, word line pulse voltage and bit line voltage are the parameters considered as test conditions. An industrial core-cell design with a 65 nm technology is used as case study.
Keywords :
MOSFET; SRAM chips; failure analysis; integrated circuit design; NBTI induced failure detection; PMOS transistors; SRAM core-cells; bit line voltage are; circuit level models; degradation phenomenon; industrial core-cell design; negative bias temperature instability; post-production test; random dopant fluctuation; size 65 nm; statistical simulation method; transistor level model; word line pulse voltage; word line pulse width; Circuits; Degradation; Negative bias temperature instability; Niobium compounds; Random access memory; Semiconductor process modeling; Space vector pulse width modulation; Testing; Titanium compounds; Voltage; NBTI; SRAM DfT; SRAM reliability; SRAM test; core-cell stability;
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-1-4244-6649-8
DOI :
10.1109/VTS.2010.5469612