DocumentCode
2426373
Title
An output compression scheme for handling X-states from over-clocked delay tests
Author
Singh, Adit ; Han, Chao ; Qian, Xi
Author_Institution
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
fYear
2010
fDate
19-22 April 2010
Firstpage
57
Lastpage
62
Abstract
Faster-than-rated clock delay tests aimed at targeting small delay defects can generate a large number of unknown X values because the test response for all paths longer than the (over clocked) test clock period must be marked X. Current test compression techniques cannot efficiently handle such a large number of X responses. We propose a simple multiplexing scheme for output test data compression which avoids any compaction of the test response. Just as input test compression techniques take advantage of the fact that there are only a small number of ¿care¿ bits in the ATPG generated test inputs, our new approach leverages the fact that not all the output bits in the captured test response need be observed. In most cases, observing only selected 2-5% of the test response bits captured in the scan chains can still result in the same target test coverage as when all output bits are observed, albeit at the expense of requiring some additional TDF delay test vectors. Since no test result compaction is performed, the new approach is capable of handling an unbounded number of X-states during aggressive delay testing. Experimental results show that test time/data volume reduction of 10X or better appears viable.
Keywords
clocks; data compression; delays; integrated circuit testing; TDF delay test vectors; X-states; faster-than-rated clock delay tests; multiplexing scheme; output compression scheme; over-clocked delay tests; test data compression; test response; Application specific integrated circuits; Automatic test pattern generation; Chaos; Circuit faults; Circuit testing; Clocks; Compaction; Delay; Integrated circuit testing; Very large scale integration; Delay test; X-values; output compression;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2010 28th
Conference_Location
Santa Cruz, CA
ISSN
1093-0167
Print_ISBN
978-1-4244-6649-8
Type
conf
DOI
10.1109/VTS.2010.5469617
Filename
5469617
Link To Document