A novel hybrid method for SDD pattern grading and selection

Small-delay defects (SDDs) have become a major concern in nanometer technology designs. Traditional timing-unaware transition-delay fault (TDF) ATPGs are not efficient in detecting SDDs since they tend to detect delay faults via shorter paths. Timing-aware ATPG tools have been proven to result in significantly large CPU runtime and pattern count. In this paper, we present a hybrid procedure that grades patterns in terms of their effectiveness in detecting SDDs and selects the most effective ones. The grading procedure is performed on a large repository of patterns generated by n-detect TDF ATPG and takes advantage of n-detect capability in detecting a delay fault n times from different paths. 1-detect TDF ATPG is performed after pattern grading and selection to ensure same fault coverage as timingaware ATPG´s is obtained. Experimental results demonstrate that our proposed hybrid method is fast and efficient; it can sensitize a greater number of longer paths with much lower pattern count and CPU runtime compared to a commercial timing-aware ATPG tool.