Abstract :
Test costs continue to rise as designs become more complex, the controllability and observability points at the chip boundary reduce, defects become more subtle making it harder to detect them, and reliability requirements become stringent. While several techniques have been developed and deployed to contain test costs to remain within acceptable limits, new technologies tend to generate excursions where the costs once again become prominent. Digital circuits have benefitted from structured test methodologies (involving DFT, ATPG and BIST) wherein different optimizations have been incorporated to reduce test costs. Analog circuits have also received wide attention due increasing analog content in today´s chips. DFT techniques for them have evolved to provide additional controllability and observability through additional on-chip / off-chip instrumentation. Digitization of the analog stimuli and response have also been considered adequate to ascertain the correctness of analog circuits. RF circuits, on the other hand, have a few characteristics which have rendered such simplification so far inadequate. (i) The stimuli and response can be greatly deformed due to attenuation at the high frequencies at which the transmission occurs over the tester channels. (ii) Multiple RF modules in a chip cause further interference, thereby impairing the measurement resolution attainable for test. (iii) While on-chip instrumentation for test and measurement is even more important, providing it itself largely uneconomical. (iv) There is virtually little automation (EDA tools, etc.) available today to address these issues. Hence, though RF circuits are just an extension of analog / mixed-signal circuits in the high frequency range, their test poses several new challenges, which have hitherto not been adequately solved.
