DocumentCode
2426699
Title
Algorithm features of hierarchical descending placement
Author
Shchebyuk, Ihor
fYear
2003
fDate
18-22 Feb. 2003
Firstpage
295
Lastpage
297
Abstract
In clause the description of descending hierarchical placement algorithm and influence of realization variants on placement results is carried out. The research is carried out on the basis of real constructives.
Keywords
circuit complexity; circuit layout CAD; parallel algorithms; algorithm realizations; binary tree; complexity; connectivities between elements; consecutive escalating; design automation; hierarchical descending placement; hierarchical placement algorithm; internal connections; macromodels; optimum convolution tree; parallel-sequential algorithms; parameters change influence; Circuits; Convolution; Terminology;
fLanguage
English
Publisher
ieee
Conference_Titel
CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of
Print_ISBN
966-553-278-2
Type
conf
DOI
10.1109/CADSM.2003.1255067
Filename
1255067
Link To Document