Title :
SER reliability of 1TRAM designs
Author :
Sinitsky, Dennis ; Peng, Sam ; Wang, James ; Ong, T.C. ; Chen, Ed ; Hsu, Fu-Chieh
Author_Institution :
Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
Abstract :
In this paper, SER reliability is analyzed for 1TRAM circuits for a wide range of parameters. The results show that as technology scales, SER of 1TRAM does not degrade as dramatically as the one of SRAM. Although for older technologies SER of 1TRAM is worse than that of SRAM, it becomes better around 0.13 μm node. Additionally, measurements and simulations indicate weak dependence of 1TRAM SER on voltage, temperature, and Qcrit.
Keywords :
integrated circuit modelling; integrated circuit reliability; integrated memory circuits; random-access storage; 0.13 micron; 1TRAM; SER reliability; simulations; temperature; voltage; weak dependence; Capacitance; Circuit analysis; Circuit simulation; Degradation; Frequency dependence; Manufacturing; Random access memory; Semiconductor device manufacture; Temperature dependence; Time measurement;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2002. 40th Annual
Print_ISBN :
0-7803-7352-9
DOI :
10.1109/RELPHY.2002.996640
