Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM

Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is an emerging type of nonvolatile memory with compelling advantages in endurability, scalability, speed, and energy consumption. As the process technology shrinks, STT-MRAM has limited sensing margin due to the decrease in supply voltage and increase in process variation. Furthermore, the relatively smaller resistance difference of two states in STT-MRAM poses challenges for its read/write circuit design to maintain an acceptable sensing margin. The proposed reference circuits optimization scheme solves the reference resistance distribution issue to maximize the sensing margin and minimize the read disturbance, with low power consumption. Simulation results show that the optimization scheme is able to significantly improve the read reliability with the presence of one or few cases of reference cell failure, thus it eliminates the requirement of additional circuits for failure detection of reference cell or referencing to neighboring blocks.