Title :
Charge trapping induced DRAM data retention time degradation under wafer-level burn-in stress
Author :
Won Seo, Hyeong Won ; Jin, Gyo Young ; Yang, Ki-Hoon ; Lee, Yun-Jae ; Lee, Joo-Hyun ; Song, Du-Heon ; Oh, Yong-Chol ; Noh, Jun-yong ; Hong, Seung-Wan ; Kim, Dong-Hyun ; Jin-Yang Kim ; Kim, Hyeong-Hoon ; Won, Dae-Joong ; Lee, Won-Seong
Author_Institution :
TD2 Project R&D Center, Samsung Electron., Yongin City, South Korea
Abstract :
This paper investigates the effects of wafer burn-in on the degradation of DRAM data retention time characteristics. The problem was characterized using a substrate electron injection method described in this paper. As a result, it could be experimentally demonstrated that the data retention time degradation was attributed to the enhanced GIDL (gate induced drain leakage) due to the increased electric field caused by electron trapping in the gate oxide during wafer burn-in stress.
Keywords :
DRAM chips; dielectric thin films; electron traps; integrated circuit reliability; integrated circuit testing; leakage currents; DRAM data retention time characteristics; GIDL; charge trapping; data retention time degradation; electric fields; electron trapping; gate induced drain leakage; gate oxide electron trapping; substrate electron injection method; wafer-level burn-in stress; DRAM chips; Degradation; Electron traps; Probability distribution; Random access memory; Research and development; Stress; Testing; Tunneling; Voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2002. 40th Annual
Print_ISBN :
0-7803-7352-9
DOI :
10.1109/RELPHY.2002.996650
