Title :
Pseudo-breakdown events induced by biased-thermal-stressing of intra-level Cu interconnects-reliability and performance impact
Author :
Song, Won S. ; Kim, Tae J. ; Lee, D.H. ; Kim, Tae K. ; Lee, Chang S. ; Kim, Jeong W. ; Kim, Sam Y. ; Jeong, Dong K. ; Park, Ki C. ; Wee, Young J. ; Suh, Bong S. ; Choi, Seung M. ; Kang, Ho-K ; Suh, Kwang P. ; Kim, Sang U.
Author_Institution :
Semicond. R&D, Samsung Electron., Co., Ltd, Yongin City, South Korea
Abstract :
The pseudo-breakdown (PBD) phenomenon has been investigated in intra-level reliability assessment of Cu-interconnects. Field and intralevel spacing dependence show that PBDs form an irreversible permanent damage path that differs from that of HBDs by the amount of Joule heat released via breakdown induced leakage path. An RC delay simulation demonstrates that PBD leakage may hinder the circuit performance with further device scale down. Physical failure analysis reveals the lower liner/IMD interface as the predominant leakage path accompanying PBDs, confirming the failure mechanism established through the local electric and stress field simulations. We propose a PBD induced leakage mechanism supported by experimental results.
Keywords :
circuit simulation; copper; electric breakdown; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; leakage currents; thermal stresses; Cu; Cu interconnects; Joule heat release; PBD; PBD induced leakage mechanism; PBD leakage; RC delay simulation; biased-thermal-stressing; breakdown induced leakage path; circuit performance; device scale down; failure analysis; failure mechanism; intra-level Cu interconnects; intra-level reliability; intra-level spacing dependence; irreversible permanent damage path; local electric field simulations; lower liner/IMD interface predominant leakage path; performance impact; pseudo-breakdown events; pseudo-breakdown phenomenon; reliability; stress field simulations; Analytical models; Circuit optimization; Circuit simulation; Delay; Electric breakdown; Failure analysis; Integrated circuit interconnections; Leakage current; Stress; Testing;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2002. 40th Annual
Print_ISBN :
0-7803-7352-9
DOI :
10.1109/RELPHY.2002.996653