Title :
Backtraced deductive-parallel fault simulation for digital circuits
Author :
Hahanov, Vladimir ; Sysenko, Iryna ; Kolesnikov, Konstantin
Author_Institution :
Comput.-Aided Design Dept., Kharkov Nat. Univ. of Radioelectronics, Ukraine
Abstract :
A fast deductive-parallel backtraced fault simulation method uses the superposition procedure, which is oriented on large digital designs. It is proposed processing of RT and gate level design representation. The data structure and program are oriented on algorithms for realization of proposed method and integration in automatic test pattern generation systems.
Keywords :
automatic test pattern generation; backtracking; combinational circuits; computational complexity; fault simulation; field programmable gate arrays; logic testing; parallel algorithms; Boolean equations; RT level design representation; automatic test pattern generation; combinational circuits; data structure; digital circuits; fast deductive-parallel backtraced method; fault simulation method; gate level design representation; large digital designs; parallel simulation; reconvergent fan-outs; structural-functional analysis; stuck-at-fault simulation; superposition procedure; truth table; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Digital circuits; Digital systems; Logic testing; Programmable logic arrays; System testing;
Conference_Titel :
CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of
Print_ISBN :
966-553-278-2
DOI :
10.1109/CADSM.2003.1255097
