DocumentCode :
2427460
Title :
Hardware implementation of Frequency Domain Link Adaptation for OFDMA based systems
Author :
Das, Sandip ; Chakrabarti, Indrajit ; Das, Suvra Sekhar
Author_Institution :
G.S. Sanyal Sch. of Telecommun., Indian Inst. of Technol., Kharagpur, Kharagpur, India
fYear :
2015
fDate :
Feb. 27 2015-March 1 2015
Firstpage :
1
Lastpage :
6
Abstract :
Frequency Domain Link Adaptation (FDLA) has been accepted as a promising technique to improve the spectral efficiency in Orthogonal Frequency Division Multiple Access (OFDMA) systems such as Long Term Evolution (LTE) and Worldwide Interoperability for Microwave Access (WIMAX). FDLA exploits the frequency domain channel variation by using adaptive bit and power loading scheme in frequency domain. In this paper, we propose a hardware efficient architecture of adaptive bit loading scheme and implement the same in FPGA. It is shown that the FPGA design provides power efficiency and lower latency implementation. The design is shown to be flexible and reconfigurable and is compatible with multiple standards with different configurations. In this work, two different FDLA algorithms are implemented. This design is implemented in Wireless Open Access Research Platform (WARP) which has virtex-4 FPGA in its core for processing. The design is tested for its over the air performance by integrating it with FPGA based MIMO-OFDMA testbed, developed on the WARP platform. Real time over the air performance results are presented for uncoded systems.
Keywords :
MIMO communication; OFDM modulation; WiMax; field programmable gate arrays; frequency division multiple access; frequency-domain analysis; FDLA system; FPGA; LTE; Long Term Evolution; MIMO-OFDMA testbed; WARP platform; WIMAX; adaptive bit loading scheme; frequency domain link adaptation; hardware efficient architecture; hardware implementation; microwave access; orthogonal frequency division multiple access system; power efficiency; power loading scheme; spectral efficiency; wireless open access research platform; Algorithm design and analysis; Bit error rate; Field programmable gate arrays; Hardware; Loading; Modulation; Signal to noise ratio; FDLA; FPGA; OFDMA; adaptive bit loading; hardware implementation; improved architecture; reconfigurable;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications (NCC), 2015 Twenty First National Conference on
Conference_Location :
Mumbai
Type :
conf
DOI :
10.1109/NCC.2015.7084895
Filename :
7084895
Link To Document :
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