Title :
Real time image segmentation using FPGA and parallel processor
Author :
Miteran, J. ; Bailly, R. ; Gorria, P.
Author_Institution :
Lab. GERE, Burgundy Univ., Creusot, France
Abstract :
We present in this paper the realization of a classification board, for real-time image segmentation. The classification of each pixel is completed using a real time extraction of attributes and a geometric classification method by stress polytope training, which ensures a high decision speed (100 ns per pixels) and good performance. The decision operator has been integrated in the form of a full custom circuit, and the extraction of parameters is performed using a single high density FPGA
Keywords :
application specific integrated circuits; feature extraction; field programmable gate arrays; image classification; image segmentation; parallel processing; real-time systems; ASIC; FPGA; decision operator; full custom circuit; geometric classification; parallel processor; parameters extraction; pixel classification; real-time image segmentation; stress polytope training; Application specific integrated circuits; Field programmable gate arrays; Image segmentation; Inspection; Laboratories; Manufacturing automation; Parameter extraction; Productivity; Sampling methods; Stress;
Conference_Titel :
TENCON '96. Proceedings., 1996 IEEE TENCON. Digital Signal Processing Applications
Conference_Location :
Perth, WA
Print_ISBN :
0-7803-3679-8
DOI :
10.1109/TENCON.1996.608801