TestBuilder - ATPG system for digital devices based on FPGA

Deterministic test generation algorithms are highly complex and time-consuming. New approaches are needed to reduce execution time and to improve fault coverage. In this work, genetic algorithms for sequential circuit test generation are offered. The genetic algorithm builds candidate test vectors and sequences, using a deductive-parallel fault simulator to compute the fitness of each candidate test. The deductive-parallel method is offered for significant improvement of fault coverage percentage and for speed up of test generators. A new hardware deductive-parallel fault simulator is developed. It combines the advantages of deductive and parallel fault simulation algorithms for digital circuits described at gate, functional and RTL levels. Experimental results shows high fault coverage for most of the ISCAS´89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator and in test generators using random selection of the initial population.